As an Senior ASIC designer, the candidate will be reporting directly to the group Manager and will work closely with other group members while interacting with other groups in the company. He/She must possess well-rounded experience in the overall ASIC flow ranging from architecture, design, and post-silicon support.

The main tasks are:

• Develop design specification of complex modules according to high level requirements
• RTL coding (Verilog / VHDL)
• Verification (test plan, simulation, verification environment, test coverage)
• Layout Support (floor planning, memory generation, etc.)
• Packaging (I/O assignment, package selection, ball assignment, etc.)
• Synthesis (Synopsys DC)
• Static Timing Analysis
• Formal Verification
• DFT (test pattern generation, BIST/SCAN, etc)
• Database management (revision control, project webpage, etc.)
• System Validation (chip qualification, board design)
• Emulation Support (FPGA partitioning, emulation spec)
• RMA Support

Technical Knowledge:

• Essential : Strong RTL coding (Verilog / VHDL) skills
• Essential : Solid experience with complex (65nm +) SoC designs including synthesis, static timing, packaging, verification, DFT
• Advantage: System level experience (board, FPGA, qualification)
• Advantage: Low power design experience
• Asset: Customer support (RMA, datasheet, etc) experience

General Criteria:

• Essential : Bachelor degree in Engineering or equivalent
• Important : 10+ years of relevant experience
• Important : Excellent English communication skills (verbally and written)
• Important : Willing to travel occasionally (-25%) for 1+wks
• Asset : Wideband wireless telecom experience

Others:

• Detail oriented

Personal skills:

• Team Player
• Self-driven and proactive

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